Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures

Multi-FPGA Architectures Vinoo Srinivasan Ranga Vemuri University of Cincinnati, Cincinnati OH 45221{0030. E-mail: fvsriniva, [email protected] Abstract This paper presents spade, a system for partitioning designs onto multi-fpga architectures. The input to spade is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. spade consists of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and rtl design space exploration heuristic. We show how various architectural constraints can be e ectively handled using an iterative partitioning engine.